1. Field of the Invention
The disclosures herein relate to a power-on reset circuit that outputs a reset release signal.
2. Description of the Related Art
A power-on reset circuit that negates a reset signal upon detecting the rise of a power supply voltage exceeding above a predetermined threshold is known in the art (see Patent Document 1, for example). FIG. 1 is a drawing illustrating a basic configuration of a related-art power-on reset circuit disclosed in Patent Document 1, for example. In the case of the circuit illustrated in FIG. 1, a comparator C1 outputs a low-level voltage signal POR immediately after the start of applying a power supply voltage VDD since a divided voltage Va obtained by dividing the power supply voltage VDD through resistors R1 and R2 is lower than a reference voltage Vref. When the power supply voltage VDD reaches a certain level, the divided voltage Va exceeds the reference voltage Vref, so that the comparator C1 outputs a high-level voltage signal POR. Namely, the circuit illustrated in FIG. 1 indicates a reset state when the low-level voltage signal POR is output, and indicates a reset release state when the high-level voltage signal POR is output.
FIG. 2 is a time chart illustrating the changes of the voltage signal POR and the power supply voltage VDD from the start to the end of applying the power supply voltage VDD in the circuit of FIG. 1. The power supply voltage VDD is controlled by a voltage control circuit such as a regulator such that the power supply voltage VDD becomes equal to a preset target voltage. In the initial stage of applying power supply voltage VDD, the voltage signal FOR generally changes from a low level to a high level in the range lower than the target voltage of the power supply voltage VDD. With such a change, the operating mode shifts from a reset mode to a reset release mode. In the end stage for the end of applying the power supply voltage VDD, the voltage signal POR changes from a high level to a low level in the range lower than the target voltage of the power supply voltage VDD. With such a change, the operating mode shifts from the reset release mode to the reset mode.
In the related-art power-on reset circuit, the voltage detected for the purpose of switching between the reset mode and the reset release mode needs to be constantly monitored from the start to the end of applying the power supply voltage VDD. Such constant voltage monitoring contributes to an increase in the current consumption by the power-on reset circuit.
Accordingly, it may be desired to provide a power-on reset circuit that can reduce current consumption.
[Related-Art Documents]
[Patent Document]
[Patent Document 1] Japanese Patent Application Publication No. 2009-123168